About

Work

Since October 2012, I have been working as a hardware design engineer in the Mobile Silicon group at Apple.

Previously, while a graduate student at Stanford, I spent the summer of 2011 as an intern at NVIDIA Research evaluating quality-of-service requirements for on-chip networks in future GPU architectures. In the course of the internship, I co-developed a detailed event-driven network simulator and integrated it into an existing execution-driven GPU simulator framework.

From 2005 to 2007, I worked as a hardware development engineer for IBM Deutschland Entwicklung GmbH in Böblingen, Germany. My job responsibilities included the design and implementation of what in IBM-speak is called "pervasive logic" (roughly, anything on the chip that is not part of mainline functionality, such as the performance monitor, timer facilities, power management, etc.) for high-performance server microprocessors. Two patents were issued based on my work at IBM.

While a student in Aachen, I worked as an intern for Siemens Corporate Research, Inc. in Redmond, WA, during the summer of 2004; the internship focused on embedded software development for a USB DECT adapter.

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Education

I completed my Ph.D. in the Department of Electrical Engineering at Stanford University in August 2012. I conducted research in computer architecture and interconnection networks under the supervision of Prof. William J. Dally; my dissertation focused on efficient router microarchitecture for on-chip networks. My research was generously supported by a Prof. Michael J. Flynn Stanford Graduate Fellowship.

In June 2005, I finished my studies at the Rheinisch-Westfälische Technische Hochschule Aachen, Germany, with a "Dipl.-Ing." degree in Electrical Engineering and Information Technology. I completed my degree with honors and received a Springorum Denkmünze award. For my diploma thesis, I investigated the use of Deterministic and Stochastic Petri Nets (DSPNs) for performance modeling in the context of Network-on-Chip architectures. The thesis was written under the supervision of Prof. Tobias G. Noll.

With the generous support of a Fulbright scholarship, I spent the 2002/2003 academic year at the University of Washington's department of electrical engineering as a visiting graduate student.

During my studies in Germany, I also received financial support through a Prof. Dr. Koepchen scholarship from 2003 to 2005, and student developer scholarships enabled me to attend Apple's yearly World-Wide Developers Conference in 2003, 2004 and 2005.

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Projects

Network-on-Chip Router Generator: I have developed a highly parameterized implementation of a state-of-the-art network-on-chip router. The router is implemented in Verilog and makes extensive use of parameters and generate statements to allow many different router configurations to be instantiated from a single code base. The generated code is fully synthesizable, and has been used in several research papers to evaluate area, power and timing for different router implementations.

BookSim 2.0: A widely used interconnection network simulator. I have made significant contributions to the BookSim interconnection network simulator developed in the CVA Group at Stanford. Among other things, I implemented combined VC and switch allocation, rewrote the router model to be event-driven, and added support for multiple traffic classes with fully independent parameters and statistics.

iScroll2: A modified trackpad driver that enables two-finger scrolling on older Apple laptops. I initially developed this for my trusty old PowerBook G4, but since the hardware has become obsolete, iScroll2 is no longer actively maintained.

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Patents

Daniel U Becker. Credit-Based Processor Energy Consumption Rate Limiting System. US 9,798,375 B1 (issued 10/24/2017). [ http ]

Daniel U Becker, Rafael Keggenhoff, Thuyen Le, Tobias Webel, Matthias Woehrle. Accounting for Microprocessor Resource Consumption. US 8,140,885 B2 (issued 3/20/2012). [ http ]

Matthias Fertig, Tilman Gloekler, Ralph C Koester, Alexander E Mericas, Thomas Plueger, Daniel U Becker. System and Method for Distributing Signal with Efficiency over Microprocessor. US 8,055,809 B2 (issued 11/8/2011). [ http ]

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Publications

Daniel U Becker. Efficient Microarchitecture for Network-on-Chip Routers. PhD thesis, Stanford University, August 2012. [ http ]

Nan Jiang, Daniel U Becker, George Michelogiannakis, James Balfour, Brian Towles, John Kim and William J Dally. A Detailed and Flexible Cycle-Accurate Network-on-Chip Simulator. In Proceedings of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software, 2013. [ .pdfdoi ]

Daniel U Becker, Nan Jiang, George Michelogiannakis and William J Dally. Adaptive Backpressure: Efficient Buffer Management for On-Chip Networks. In Proceedings of the 30th IEEE International Conference on Computer Design, 2012. [ .pdfdoi ]

Nan Jiang, Daniel U Becker, George Michelogiannakis and William J Dally. Network Congestion Avoidance through Speculative Reservation. In Proceedings of the 18th International Symposium on High-Performance Computer Architecture, 2012. [ .pdfdoi ]

George Michelogiannakis, Nan Jiang, Daniel U Becker and William J Dally. Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011. [ .pdfdoi ]

George Michelogiannakis, Nan Jiang, Daniel U Becker and William J Dally. Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. IEEE Computer Architecture Letters, 2011. [ httpdoi ]

George Michelogiannakis, Daniel U Becker and William J Dally. Evaluating Elastic Buffer and Wormhole Flow Control. IEEE Transactions on Computers, 60(6):896-903, 2011. [ httpdoi ]

Nan Jiang, Daniel U Becker, George Michelogiannakis and William J Dally. Performance Implications of Age-Based Allocation in On-Chip Networks. CVA Technical Report 129, 2011. [ .pdf ]

George Michelogiannakis, Nan Jiang, Daniel U Becker and William J Dally. Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. CVA Technical Report 128, 2011. [ .pdf ]

Daniel U Becker and William J Dally. Allocator implementations for network-on-chip routers. In Proceedings of the 2009 ACM/IEEE Conference on High Performance Computing, Networking, Storage and Analysis, 2009. [ .pdfdoi ]

Holger Blume, Thorsten von Sydow, Daniel U Becker and Tobias G Noll. Application of deterministic and stochastic petri-nets for performance modeling of noc architectures. Journal of Systems Architecture, 53(8):466-476, 2007. [ .pdfdoi ]

Holger Blume, Thorsten von Sydow, Daniel U Becker and Tobias G Noll. Modeling noc architectures by means of deterministic and stochastic petri nets. In Embedded Computer Systems: Architectures, Modeling, and Simulation, volume 3553 of Lecture Notes in Computer Science, pages 374-383. Springer Berlin / Heidelberg, 2005. [ .pdfdoi ]

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Talks

Adaptive Backpressure: Efficient Buffer Management for On-Chip Networks. Presented at ICCD '12, Montreal, QC, Canada, Sep. 30;-Oct. 3, 2012. [ .pptx ]

Efficient Microarchitecture for Network-on-Chip Routers. Thesis defense talk, Stanford, CA, Aug. 21, 2012. [ .pptx ]

Allocator Implementations for Network-on-Chip Routers. Presented at SC '09, Portland, OR, Nov. 14-20, 2009. [ .pptx ]

Networks on Chip: Router Microarchitecture & Network Topologies. Presented at ST Microelectronics, Crolles, France, Oct. 13, 2009. [ .pptx ]

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Class Projects

Daniel U Becker, David B Sheffield, Vishal Parikh. Instruction Compounding for Embedded Microprocessors. Stanford EE382A Class Project, Prof. Kozyrakis, Spring 2008. [ .pdf ]

Daniel U Becker, Hakan Baba. Error Detection Using Gate-Level Assertions. Stanford EE386 Class Project, Prof. Mitra, Spring 2008. [ .pdf ]

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Contact

You can reach me at dub@doemail.org.

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